`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:42:48 05/04/2013 
// Design Name: 
// Module Name:    ALU 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALU #(parameter N = 4) (
    input SUM,
    input CMP,
    input MUL,
    input [N - 1: 0] REGA,
    input [N - 1: 0] REGB,
    output [(2 * N) - 1: 0] d_out
    );
	 
	 wire [(2 * N) - 1 : 0] ADD_out;
	 wire [(2 * N) - 1 : 0] CMP_out;
	 wire [(2 * N) - 1 : 0] MUL_out;
	 reg [(2 * N) - 1 : 0] out;
	 
	 Adder #(.N(4)) ADDER (.a_in(REGA),
									.b_in(REGB),
									.d_out(ADD_out)
									);
	 Compare #(.N(4)) COMPARE (.a_in(REGA),
								  .b_in(REGB),
								  .d_out(CMP_out)
								  );
	 Multiplier #(.N(4)) MULTIPLIER (.a_in(REGA),
									  .b_in(REGB),
									  .d_out(MUL_out)
									  );
	
	always @(*) begin
		if (SUM) out <= ADD_out;
					
		else if (CMP) out <= CMP_out;
					  
		else if (MUL) out <= MUL_out;
		
		else out <= 8'h00;
	end
	
	assign d_out = out;


endmodule
